Since the 1940s, when the printed circuit board emerged, development of new electronic packages has been associated with a continuous increase in circuit density.
To satisfy this requirement and to enable adequate realization of performance advantages, associated with modem VLSI semiconductor devices, multichip module technology has been developed, providing for an increase in interconnection density, accompanied by simultaneous size reduction of the package.
Despite the first multichip modules having emerged in the late 1970s, this technology is developing very extensively, and today there are known numerous multichip modules and various methods for their manufacturing, which are described in different publications, including books, patents, scientific articles, catalogs, etc.
A comprehensive survey of multichip module technology can be found, for example, in the monograph "Thin film multichip modules" by George Messner, Iwona Turlik, John W. Balde and Philip E.Garrou, edited by the International Society for Hybrid Microelectronics, 1992.
In accordance with basic definition and classification, given in this monograph the multichip module is a device, which provides the interconnections for several chips that are subsequently protected by a coating or an enclosure.
In accordance with different approaches and fabrication techniques the MCMs known today can be divided into 3 main groups:
MCM-C are multichip modules which use sinterable metals to form the conductive patterns of signal and power layers, which are applied onto a substrate made of ceramic or glass-ceramic material PA1 MCM-L are multichip modules which use laminate structures and employ printed circuit technologies to form a pattern of signal and power layers, which are applied onto layers made of organic insulating material. PA1 MCM-D are multichip modules on which layers of metal and insulator are usually formed by the deposition of thin film onto a rigid support structure usually made of silicon, ceramic, or metal. PA1 a) for the via zone: .DELTA.1 denotes the via etch depth, t the thickness of the conducting layer and the planarity degree (PD) in % is PDv=.DELTA.1/t*100. It can be readily understood, that degree of planarity is better as PD value diminishes. PA1 b) for the conductor zone: .DELTA.2 denotes the difference in thickness of adjacent conductive and nonconductive regions; degree of planarity is defined in similar manner as PDc=.DELTA.2/t*100. PA1 formation of a first photoresist mask onto the aluminium layer PA1 etching of the aluminium layer and removing the mask PA1 forming a second photoresist mask and formation of vias PA1 subsequent anodic oxidation of exposed regions of aluminium layer and removing the photoresist mask PA1 complete covering with a new aluminium layer PA1 simultaneous etching of a new aluminium layer and of anodically oxidized regions so as to achieve planarization of oxide and nonoxide regions. PA1 masking of at least one selected portion of the surface of said electrically conductive layer so as to form a first mask thereon said mask being provided with the appropriate preselected pattern so as to hide the first group of selected locations of said layer and to expose the second group of selected locations thereof, PA1 selective oxidation, directed substantially in depth of said electrically conductive layer via said mask so as to convert said exposed selected locations, and bulk of said layer situated therebeneath into nonconductive regions without, however oxidation of said selected hide locations so as to leave situated therebeneath the bulk of said layer as conductive regions. PA1 removing said first mask so as to enable planarization of levels of said oxidized electrically nonconductive regions with levels of nonoxidized electrically conductive regions. PA1 covering said planarized conductive and nonconductive regions by an additional initially continuous electrically conductive layer, PA1 repeating said main sequence of steps, while masking each additional layer with a mask having a preselected pattern, preferably different from that of said first mask. PA1 voltage is progressively increased with constant gradient 1-2 v/sec from 0 up to 40 v PA1 oxidation is maintained at constant voltage until establishing a current density of 1-2 amper/dm.sup.2, corresponding to formation of oxidised regions, transversely extending in depth of respective initially continuous layer. PA1 voltage is progressively increased with constant gradient 1-2 v/sec from 0 up to 150-300 v PA1 oxidation is maintained at constant voltage for a period of time, sufficient for establishing a current density of 0,05-0,07 amper/dm.sup.2, corresponding to the formation of oxidised regions, transversely extending in depth of respective layer. PA1 at least one first layer, consisting of a plurality of electrically conductive regions, interspersing with electrically nonconductive regions; said regions are arranged in accordance with preselected pattern and extend laterally and transversely within said layer PA1 said electrically conductive regions are made of metallic material, preferably of aluminium; said electrically nonconductive regions constitute a product of the conversion of said metallic material in electrically nonconductive form thereof, preferably alumina. PA1 said conductive and nonconductive regions extend in depth of said layer, substantially transversely with respect to the outwardly facing surface thereof and are substantially co-planar therebetween.
FIG. 1 illustrates schematically the structure arranged on a substrate of a general type MCM. This structure includes electrically conductive regions (signal layers, conductor, power layer) and insulating regions arranged in accordance with certain pattern on the substrate.
The conductive regions, referring to adjacent layers can merge so as to form so-called vias.
Parameters, which are of importance for the performance of such an MCM include, inter alia, material of an electrically conductive region, the thickness of the respective layer t and width thereof and degree of planarisation of adjacent layers. The last two parameters are shown schematically on FIG. 2 presenting an enlarged part of the structure illustrated in FIG. 1 and referring to known, in the prior art, MCM structures and particularly to a typical Polyimide or SiO2 MCM.
One can see that there are two types of nonplanarity inherent to this structure. The first type is associated with the via zone; the second one with the zone adjacent to any insulating region (conductor zone). Despite the fact that in FIG. 2 only one set of conductor-insulator layers is shown it should be understood, that in practice a multilayered structure can be realized. The degree of planarity will be defined as follows:
FIG. 3 shows schematically parameters presented in FIG. 2 in connection with the present invention and it will be shown further how these parameters can be improved by virtue of the present invention. Here t refers to thickness of regions belonging to first conductive layer (conductor) and .DELTA.1 and .DELTA.2 refers respectively to degree of nonplanarity of insulating region (insulator) in a via zone and in a conductor zone.
Each of the above listed MCMs is defined by structural parameters, inherent to general structure, shown in FIG. 1, however characteristics of these parameters are different, depending on the particular type of MCM. Each of them has its own advantages and disadvantages with respect to manufacturing costs and performance.
Table 1 below compares typical dimensional and structural parameters of L-, C- and D-type MCM's.
TABLE 1 ______________________________________ MCM-L MCM-C MCM-D ______________________________________ Substrate Material Organic Alumina Silicon Alumina Electrical conductive regions Material Cu W/Mo, Ag/Pd Cu/Al t -Thickness 10-50 20-50 1-5 (micron) w -Width 75 100 10 (micron) Electrical insulating regions Material Organic Alumina PI t -Thickness 200-500 50-100 10-70 (micron) Via 150 100-200 25 (micron) Dielectric Constant 4-5 7 4 ______________________________________
The present invention will be disclosed further in connection with the last category of MCMs, i.e. MCM-D's made by the thin film fabrication method, in which a continuous thin film consisting of metallic material, is treated so as to convert selected regions thereof into dielectric regions. It will be shown further how by virtue of the present invention the above mentioned parameters, listed in table 1 and inherent to known MCM-D's are improved.
One of popular methods for the manufacture of MCM-Ds is based on the formation of dielectric polyimide layers onto patterned metallic layers (usually Cu, Al) with typical thickness of 1-3 microns, by means of spinning and subsequent curing and polymerization thereof.
Despite the relatively high degree of planarity of the insulating regions achieved within the polyimide layers adjacent to conductor zones (low value of .DELTA.2) this method is associated with inherently insufficient planarization of the via zones (high value of .DELTA.1), which my result in limited resolution and inferior performance.
Moreover it should be pointed out that poor thermal conductivity of polymeric materials is insufficient for utilization of chips, in which functioning is associated with substantial heat generation.
It should be pointed out that planarization is extremely critical for the reliable performance of MCM structures and required degree thereof can be obtained in this method only through the use of expensive planarizing organic dielectric material or by mechanically or chemically polishing (etching away) the dielectric surface until a planar surface is obtained.
The inevitable consequence of these additional operations is associated with increased cost and reduced yield, since these operations may impair thin film surface structure and therefore a very thorough and sophisticated testing procedure might be required to ensure reliable performance of such a structure. An example of such a fabrication method can be found in U.S. Pat. No. 5,055,907, assigned to Mosaic Inc.
Another known method for manufacturing MCM-Ds is based on the depositing of SiO2 film, which serves as an insulating barrier, separating between adjacent metallic conductive layers.
The disadvantage of this method lies in the necessity to carry out separately the via formation step and is associated therefore with extra costs and reduction in yield.
It should be pointed out, that the degree of planarization, ultimate via diameter and resolution, achievable in this method, are limited.
An additional disadvantage, inherent to this method, is associated with employing of a chemical reagent such as fluoric acid, which is dangerous. Special measures may also be required for the prevention of environmental pollution problems.
There is also mother known method for the manufacture of MCM-Ds It is based on the formation of thin films, consisting of interspersing regions of dielectric alumina and aluminium created within a substrate made of aluminium. This method is disclosed in the East German Patent DD 281076, assigned to VEB ROBOTRON-BUCHUN.
The multichip module, described in this document comprises a ceramic substrate and applied thereon upper layers of aluminium provided with an Al-conductor pattern, formed by etching through a mask. This pattern includes conductive regions, insulated there between by nonconductive aluminium oxide regions, formed by spark discharge anodic oxidation.
The manufacturing method, used for fabrication of this MCM-D is based on so called subtractive etching through a patterned layer of photoresist and is defined by repetition of the following main sequence of steps:
The known process is complicated and costly.
The other drawback, inherent to this method is associated with the necessity of subtractive etching, which permits only limited degree of planarization, since this procedure might deteriorate the thin film surface.
The inherent drawback, associated with etching is obtaining of sidewalls, sloping by 45 degrees and therefore compromising the maximum density of functional track, created within the same layer.
Furthermore, since the etching procedure usually requires relatively strong acids, it can be assumed that practical implementation of this manufacturing process will be associated with complicated measures which are necessary to prevent environment pollution.
It should be pointed out, that the spark erosion process does not allow for obtaining of oxided regions with a thickness of more than 0,1 micron, which might be insufficient for electrical insulation in some cases.